1) Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, to a bonding pad electrode structure and to a bond pad structure that prevents generation of cracks derived from mechanical stress from wire bonding.
2) Description of the Related Art
Integrated circuits must be electrically contacted. The electrical connection from the external pins of the integrated circuit package to the integrated circuit goes through bond pads which are located on the periphery of the integrated circuit. The bond pads are metal areas which are electrically connected to the devices in the integrated circuit via and electrically conducting wiring layers (e.g., Metal layers). Due to conventional bonding technology used to, for example, attach wires to the bond pads and to design constraints, the bond pads have relatively large dimensions as compared to the device dimensions and occupy or cover a significant portion of the chip surface. The area underneath the bond pads thus occupies a substantial fraction of the entire chip surface.
The electrical connection between the package and the bond pad requires physical integrity as well as high electrical conductivity. The conventional bonding process used to form the connection typically requires either or both elevated temperatures, high pressures and ultrasonic energy to produce a good connection between the wire and the bond pad. If the bond pad is on a dielectric, the bonding conditions produce mechanical stresses in the dielectric. The stress may cause defects which result in leakage currents through the dielectric between the bond pads and the underlying substrate, which is frequently electrically conducting. The leakage currents preclude use of the substrate area under the bond pads for device purposes thereby decreasing the efficiency of substrate utilization for device purposes.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,084,752 (Satoh et al.) that shows an embodiment a bonding pad comprising a buffer layer.
U.S. Pat. No. 4,636,823 (Abe) shows a bond pad over a polysilicon layer.
U.S. Pat. No. 5,149,674 (Freeman, Jr. et al.) shows bond pad.
U.S. Pat. No. 5,751,065 (Chittipeddi et al.) shows a bond pad.
U.S. Pat. No. 5,923,088 (Shiue et al.) shows a bond pad structure.
U.S. Pat. No. 6,020,647 (Skala et al) reveals a bond pad structure with patterned features.
U.S. Pat. No. 5,502,337 (Nozaki) shows a bonding pad with multiple interconnect layers.
However, there is a need for an improved bonding pad.